The present invention describes an improved fusion bonding technique for fabricating Silicon-On-Insulator (SOI) devices, such as piezo-resistive devices. Reference is first made to U.S. Pat. No. 5,286,671, entitled “FUSION BONDING TECHNIQUE FOR USE IN FABRICATING SEMICONDUCTOR DEVICES”, issued Feb. 15, 1994, to A. D. Kurtz et al., which is assigned to the assignee hereof, Kulite Semiconductor Products, Inc. The entire disclosure of U.S. Pat. No. 5,286,671 is hereby incorporated by reference as if being set forth in its entirety herein.
Therein, P++ implanted regions are bonded to an oxide layer on top of a silicon carrier wafer. The disclosed process is, however, limited in its ability to provide for very fine pattern linewidths, such as those found in piezoresistive patterns. The disclosed process also introduces enough roughness into the finished bonding surface so as to limit the thickness of the dielectric (oxide) layer in the substrate wafer to about 2000 Å-3000 Å. This undesirably limits some performance capabilities of fabricated devices and also results in less than ideal yields and increased wafer processing costs. It is desirable to overcome these limitations.